Hot-Carrier Device Degradation Modeling and Extraction Methodologies

ABSTRACT

The present invention is directed to a number of improvements in methods for hot-carrier device degradation modeling and extraction. Several improvements are presented for the improvement of building device degradation models, including allowing the user to select a device parameter used to build the device degradation model independent of the device parameter selected. The user can also select the functional relation between stress time and degradation level. To further improve accuracy, multiple acceleration parameters can be used to account for different regions of the degradation process. Analytical functions may be used to represent aged device model parameters, either directly or by fitting measured device parameters versus device age values, allowing devices with different age values to share the same device model. The concept of binning is extended to include device degradation. In addition to a binning based on device width and length, age is added. In an exemplary embodiment, only devices with minimum channel length have degraded models constructed. The present invention also allows the degradation of one device parameter to be determined based on an age value derived from another parameter. In yet another aspect, a degraded device is modeled as a fresh device with a voltage source connected to a terminal.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a Continuation in Part of U.S. patent applicationSer. No. 09/832,933, filed on Apr. 11, 2001, is related to a U.S.application entitled “Hot-Carrier Reliability Design Rule Checker”,filed concurrently with the present application, and claims priorityfrom provisional U.S. patent applications: Ser. No. 60/236,865, entitled“Hot-Carrier Circuit Reliability Simulation”, filed 29 Sep., 2000;60/236,587, entitled “Hot-Carrier Device Degradation Modeling andExtraction Methodologies”, filed 29 Sep., 2000; and 60/236,586, entitled“Hot-Carrier Reliability Design Rule Checker”, filed 29 Sep., 2000.

The above referenced applications are incorporated herein by referencefor all purposes. The prior applications, in some parts, may indicateearlier efforts at describing the invention or describing specificembodiments and examples. The present invention is, therefore, bestunderstood as described herein.

FIELD OF THE INVENTION

This invention relates generally to a design aiding apparatus andmethods for the design of integrated circuits, and, more specifically,to methods for simulating the time degradation of a circuit and itscomponents.

A portion of the disclosure of this patent document may containmaterials that are subject to copyright protection. The copyright ownerhas no objection to the facsimile reproduction by anyone of the patentdocument or the patent disclosure, as it appears in the Patent andTrademark Office patent files or records, but otherwise reserves allcopyright rights whatsoever.

BACKGROUND OF THE INVENTION

Complementary metal oxide semiconductor (CMOS) circuits may containthousands or millions of transistors and other circuit elements. Thedesign of such circuits is extremely complicated and usually employssimulators, such as SPICE, to predict circuit operation. In addition topredicting the operation of the circuit when it is new, it is frequentlyimportant to simulate the operation of the circuit as it ages fromprocesses such as hot carrier effects.

FIG. 1 is a schematic of a field effect transistor, the example herebeing a P-channel MOSFET formed on a silicon substrate, although much ofthe following discussion applies NMOS transistors and other insulatedgate devices. This device may also have a lightly doped drain (LDD)region that is not shown in FIG. 1. Some of the particulars for the NMOScase will be discussed later. The transistor 10 has a bulk N-type region5, source region 11 and drain region 12 defined at and below thesubstrate surface, and a lightly doped N-type channel region 15 having amanufactured length L_(M) in the region between the source 11 and thedrain 12. Over the channel region is an oxide or other insulating layer14 that supports the gate 13. (Here the gate is shown doped as N+,although in a PMOS this may alternately be P+.) When the transistor isturned on, current flows through the channel region below theoxide/silicon interface.

With operation over time, the PMOS transistor 10 will suffer degradationdue to device aging. An important mechanism in the aging of insulatedgate devices is the “hot carrier” effect. When the transistor is turnedon, a current I_(ds) of energized charge carriers flows through thechannel 15 from the source 11 to the drain 12. Impact of these chargecarriers near the channel/drain juncture generates electron-hole pairs.Some of the resultant electrons have sufficient energy to pass throughthe insulating layer 14 by tunneling or other leakage mechanisms and arethen collected at the gate 135 resulting in a gate current I_(G). Therest of the electrons result in a substrate current I_(sub)contribution, with generated holes adding to the drain current I_(ds).Some of the impact induced electrons become trapped inside of theinsulating layer 14 or become trapped at the interface of the channel 15and the insulating layer 14. This attracts holes to the channel side ofthe channel/insulator interface, which cause the effective boundary ofthe P+ drain region 12 to shift closer to the source region. This isshown in FIG. 2, where drain is extended by the region 12′, shorteningthe effective channel length to L′

L_(M). Additionally, the oxide/silicon interface above channel region isdamaged by the more energetic holes and electrons.

These effects degrade the transistor's operation in several ways. Asthese charges accumulate, the voltage needed at the gate to turn on thetransistor, the device's threshold voltage V_(th), changes, resulting inpositive shift, ΔV_(th)>0. This makes the PMOS threshold voltage lessnegative and reduces the V_(th) value at which the onset of leakagecurrent is seen. When a sufficient number of trapped electrons aredistributed over the manufactured length L_(M) of the channel 15, arelatively large leakage current will flow through the transistor evenwhen the gate voltage V_(G) is set to an “off” level.

The damage to the interface results in a lower mobility, μ, as thecarriers flow form source 11 to drain 12. The lower mobility results inmore resistance and lowers I_(ds), where as the electrons trapped in thedielectric tend to raise the PMOS's I_(ds) curve. The strength of theseeffects depend differently on bias conditions, but traditionally thechange due to lower mobility has been smaller; however, as device sizeshave decreased, this interface damage becomes more significant and,depending upon bias conditions, often becomes the larger effect below aquarter micron or so.

These problems are aggravated as device sizes decrease into thesubmicron region. One reason is that an amount of incursion of theregion 12′ that produces a relatively small relative change for achannel length of, say, L_(M)≈1.5 μm becomes a much larger relativechange at L_(M)≈0.25 μm. For example, if 12′ extends an absolutedistance of 0.05 μm, this produces a change of

(L′−L _(M))/L _(M)=−20%

for the shorter channel length, but of only −3% at the longer length.Another reason is that as the electric field in the channel is given by

E=V _(ds) /L,

the resultant field strength, and consequently the number ofelectron/hole pairs produced, increases greatly in a submicron deviceeven at low power operation. For example, in a L_(M)≈0.25 μm MOSFEToperating at 2.5 volts results in fields of ≈10⁷ V/m. As L′ departsfurther and further from L_(M), the field strengths increase resultingin an even greater electron/hole pair production rate.

In the case of an NMOS transistor, the results of hot-carriers differ inseveral respects. Electrons will again be trapped in the dielectric andas the number of electrons in the oxide increases, a positive shift involtage will again be needed at the gate to turn on the transistorresults, ΔV_(th)>0. As V_(th) is positive now, the threshold voltagebecomes larger in magnitude and the I_(ds) curve is lowered as the gatevoltage must additionally overcome the negative charge embedded in thedielectric to cause the channel inversion.

The damage to the interface again lowers the mobility, μ, as theelectrons flow form source 11 to drain 12, resulting in more resistanceand lowering I_(ds). Thus in this case, both effects move the I_(ds)curve in the same direction. Also as with the PMOS, the strength ofthese effects depends differently on bias conditions, with the changedue to lower mobility traditionally smaller but becoming increasinglyimportant as device size shrink. Unlike the PMOS, though, the effectivechannel length does not decrease.

These hot electron effects build up over time causing the device todegrade as it ages. To determine the aging of a circuit as a whole, thedegradation of the various devices within the circuit must beconsidered. As an example, consider the simple circuit shown in theschematic of FIG. 3, consisting of three inverters manufactured to beidentical.

FIG. 3 shows three inverters, 20 a, 20 b, and 20 c, connected inparallel with a capacitive load C 25 a, 25 b, and 25 c connected to theoutput of each. Each of these inverters consists of a circuit like thatof FIG. 4, with a PMOS transistor P_(a) 21 and an NMOS transistor N_(a)22 connected as shown. To simulate the fresh circuit, a circuitsimulation, such as of the SPICE or timing simulation type, can beperformed using the same model card for each of PMOS transistors 21 andthe same model card for each of the NMOS transistors.

To simulate the aged circuit, a model card representing the agedbehavior of each of the elements needs to be used. To determine how theaged device will operate, the device is stressed to obtain the agingmodel information from the electrical test data. From this, the agedmodel card for the device can be extracted. However, the same aged modelcard can no longer be used for all of the similar devices. To see why,consider FIG. 3 again.

The amount of degradation in the PMOS 21 and the NMOS 22 of inverter 20a depends on the input signal supplied at node X, while the degradationin inverters 20 b and 20 c will instead depend on the input at nodes Yand Z, respectively. The waveforms at these nodes will differ from eachother as the input waveform will change in both shape and magnitude asit propagates through the circuit. Thus, if the operation of a circuitafter, say, 5 years, of use is simulated, the relative amount ofdegradation in each of the inverters will differ and, consequently, adifferent aged model card will be needed for each of the transistors.For even the simple circuit of FIGS. 3 and 4, this results in athree-fold increase in the required number of model cards for the agedcircuit simulation compared with the fresh circuit. As a real circuitwill often contain thousands or even millions of elements, thesimulation of the aging of such circuits is a extremely complicatedprocess for which a large number of improvements are desirable.

SUMMARY OF THE INVENTION

The present invention is directed to a number of improvements in methodsfor hot-carrier device degradation modeling and extraction. According toa first aspect, several improvements are presented for the improvementof building device degradation models. The user can select the deviceparameter used to build the device degradation model and the selecteddevice parameter is used to extract device degradation model parametersthat will be used for general device parameter degradation. The user canalso select the functional relation between stress time and degradationlevel. In some cases it may be unnecessary to extract voltageacceleration parameters. To further improve accuracy, improved valuesfor one or more acceleration parameters can be extracted again. The useof multiple acceleration parameters can be used to account for differentregions of the degradation process.

Another aspect of the present invention provides analytical functions torepresent degraded device model parameters. In a first embodiment thisis done building degraded device models and using these to obtain thedegraded device model parameters. In a second embodiment, the analyticrepresentation of the model parameters is found by fitting measureddevice parameters versus device age values. In either case, this allowsdevices with different degradation values to share the same devicemodel.

In a further aspect of the present invention, the concept of binning isextended to include device degradation. In addition to a binning basedon device width and length, degradation is added. In an exemplaryembodiment only devices with minimum channel length have degraded modelsconstructed.

An additional aspect of the present invention allows the degradation ofone device parameter to be determined based on a degradation level valuederived from another parameter. In this way, the degradation for manydevice parameters can be determined based on a single extraction of atime acceleration parameter.

In yet another aspect, a degraded device is modeled as a fresh devicewith a voltage source connected to a terminal. This can be combined witha current source connected between terminals of the fresh device to moreaccurately represent the degraded device.

Additional aspects, features and advantages of the present invention areincluded in the following description of specific representativeembodiments, which description should be taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic drawing of a MOSFET transistor.

FIG. 2 shows the effects of aging due to the “hot-carrier” effect in thedevice of FIG. 1.

FIG. 3 is a schematic of a simple circuit used to discuss the effects ofaging on a circuit.

FIG. 4 is a detail of the circuit of FIG. 3.

FIG. 5 is a flow chart of hot-carrier circuit simulation.

FIG. 6 shows multiple current sources to represent different degradationmechanisms for a MOSFET.

FIG. 7 is a block diagram of an interface for use in hot-carrier orother aging simulation.

FIG. 8 shows the entry of MOSFET in a netlist converted to aparameterized aged device model subcircuit call.

FIG. 9 is a flow chart for building a device degradation model.

FIG. 10 shows a typical relation between device degradation and deviceage.

FIG. 11 is a flow chart of a first embodiment for building degradeddevice model.

FIG. 12 shows exemplary fresh and degraded current vs. voltage curves.

FIG. 13 is a schematic representation of degraded model files.

FIG. 14 is a flow chart of a second embodiment for building degradeddevice model.

FIG. 15 is a flow chart of a first embodiment for building a degradedbinning model.

FIG. 16 illustrates the concept of binning.

FIG. 17 is a flow chart of a second embodiment for building a degradedbinning model.

FIG. 18 is a flow chart for the binning using the first embodiment forbuilding a degraded binning model.

FIG. 19 is a flow chart for the binning methodology of the secondembodiment for building a degraded binning model.

FIG. 20 is a flow chart for generating degradation on any deviceparameter.

FIG. 21 shows an embodiment for representing a degraded device as afresh device combined with a voltage source connected to a terminal.

DESCRIPTION OF REPRESENTATIVE EMBODIMENTS

The different aspects of the present invention will be presented in thevarious sections below. Although the discussion is mainly in terms ofdevice age due to hot carriers, this process can be based on anyintermediate quantity indicative of the level of device degradation andnot just “age”; but to simplify the terminology, the discussion below ismostly presented in terms of the common case of age. In addition, thetechniques generally apply to circuit degradation due to the degradationof its constituent devices from mechanisms other than hot carriereffects.

Hot-Carrier Circuit Simulation

The various aspects of the hot-carrier circuit simulation portion of thepresent invention will be described with respect to the flow chart ofFIG. 5. As described in the following, this flow differs from the priorart methods, such as presented in U.S. Pat. No. 6,278,964, entitled “HotCarrier Effect Simulation for Integrated Circuits”, which is herebyincorporated by reference, in some of the steps included as well as inthe details of some of the steps that are found in the prior art.

Step 101 provides the netlist describing the circuit that will have thesimulation controlling commands and reliability parameters of thepresent invention. This will include the various connections of thecircuit elements and model cards for these elements as well as the agemodels. The age models may be those that are described below in the“Modeling and Extraction Methodologies” section. In one improvement overthe prior art, multiple hot-carrier circuit simulations can beaccomplished in one run with one circuit simulation by setting properhot-carrier simulation commands. This will improve simulationefficiency.

In the prior art flow, each run of a hot-carrier circuit simulationwould require a complete run of all of the steps in the flow. Forexample, to simulate the operation of the circuit and determine itsdegradation after, say, 5 years and 10 years, a complete simulationwould be performed for each of these values. Referring to FIG. 5, step107 typically consumes by far the most time. By combining the simulationfor multiple values, all of these stress times can be simulated withjust one run of step 101-107. Although steps 109, 111, and 113 will eachbe performed for each parameter, by only requiring one simulation forthe early steps—and particularly step 107—efficiency is greatlyimproved.

Another improvement of the present invention found in step 101 is thatdifferent device lifetime criteria can be applied for different circuitblocks, circuit block types, devices, device models, and device types inone or multiple hot-carrier circuit simulations. Examples of differentlifetime criteria include using parameters such as I_(ds) at differentbias conditions, device transconductance, threshold voltage, modelparameters, and so on for determining the amount of degradation. Thesecriteria are parameters measurable before and after a circuit element isstressed and that are computable to use as a gauge of devicedegradation. The different criteria can be important in different areasof the circuit. For example, a circuit may contain both an analog blockand a digital block of elements. The important degradationcharacteristics of these blocks may differ, with, say, transconductanceG_(m), V_(th), or some other voltage behavior being used in the analogelements while for a digital part it would be driving capability ofI_(ds) or the circuits delay or speed. The different criteria can beimportant in determining individual device lifetime and setting athreshold value below which the device becomes unacceptable for circuitperformance requirements, for example, when I_(ds) or G_(m) at some biasis degraded below a certain value.

Even when circuit blocks are of the same type, such as both being addersor inverters, different criteria can be applied if the degradation ofthe blocks can best be quantified by different parameter values. Thesecriteria may be different device parameters, such as the gain G_(m) orthreshold values V_(th), or the same parameter but with differentvalues, say a V_(th) shift of 100 mV in one block and 200 mV in another.

Similarly, differing criteria can be used for different devices, withsay one criterion for PMOS and one for NMOS as these may have differingdegradation mechanisms; for different models of the same device, such asan NMOS with different model cards due to, say, different sizes; or fordifferent device types, as the important criteria for a MOSFET differfrom those of a diode, which both differ from those of a bipolarjunction transistor, and so on. For example, while driving capabilitymay be important for both NMOS and PMOS devices within a given circuitblock, leakage current may only be important for a PMOS in anotherblock; or while driving capability may be the important quantity inMOSFETs, in a bipolar junction transistor the important performancecriterion may be, say, emitter-base leakage current or current gain,β=I_(c)/I_(d).

At step 103, the device degradation screening means allows a user toassign different amounts of device age, degradation and/or lifetime fordifferent circuit blocks, circuit block types, devices, device models,and device types in absolute or relative scales. For those devices whichhave pre-specified degradations, the computation of their degradationscan be skipped. Relevant device characterizations (shown in step 105)can also be skipped. This will improve simulation efficiency and reducememory usage. This step is optional.

For example, in a circuit with an analog block and a digital block, itmay be found that the analog block does not limit circuit life. The usercould set this block as already having a specific absolute degradationvalue for better speed. Alternately, as a PMOS device usually suffersless degradation than an NMOS, the user could assign a smaller relativescale: If an NMOS ages amount x, the corresponding PMOS would age α·x,where α<1 is a proportionality parameter. In the circuit of FIGS. 3 and4, setting a relative PMOS value would cut the transistor degradationcalculations in half as the value used for PMOS 21 would be obtainedfrom that of NMOS 22 instead of requiring a independent calculation.

The device degradation characterization means of step 105 is an optionalstep that characterizes the device degradation building tables which canbe used during hot-carrier circuit simulation for device age,degradation and lifetime computations. The tables can be built duringthe hot-carrier circuit simulation or as part of a stand-alone process.In a stand-alone, a new table can be produced as part of a partialsimulation ran for this purpose or be provided from another source. Thetables can also be re-used for further simulations.

Different forms of table can be built. The ART (Age Rate Table) approachis one of the forms which builds a device age rate table under variousbias conditions and which makes the device age calculation moreefficient. Some other forms, such as an I_(sub) table, an I_(gate)table, and I_(sub)/I_(ds) table for MOSFET transistors eliminate theneed of I_(sub) and/or I_(gate) calculation which reduces thecomputation cost of MOSFET device degradation.

For example, the change in device age over a time δt due tohot-electrons may be expressed in one model for an NMOS as

${{\delta \mspace{14mu} {{Age}(t)}} = {\frac{I_{ds}}{WH}\left( \frac{I_{sub}}{I_{ds}} \right)^{m}\delta \; t}},$

where H and m are the model's device degradation parameters and W is thedevices channel width, and for a PMOS as

${{\delta \mspace{14mu} {{Age}(t)}} = {\left\lbrack {{W_{g} \times \frac{1}{H_{g}}\left( \frac{I_{gate}}{W} \right)^{mg}} + {\left( {1 - W_{g}} \right) \times \frac{I_{ds}}{WH}\left( \frac{I_{sub}}{I_{ds}} \right)^{m}}} \right\rbrack \delta \; t}},$

where H_(g) and mg are degradation parameters to include the gatecurrent of the PMOS and W_(g) is a weighting parameter. The age rate inthe NMOS aging model above is then

${{rate} = {{\delta \mspace{14mu} {{{Age}(t)}/\delta}\; t} = {{\frac{I_{ds}}{WH}\left( \frac{I_{sub}}{I_{ds}} \right)^{m}} \neq {f(t)}}}},$

that, for a sufficiently small δt, is a time invariant quantity that canbe saved as a table. These formulae show how the current ratios arerelated to the device's age and that the larger the stress time t, thegreater the age. For example, as these currents are functions of thebias voltages, I_(ds), I_(sub)=f(V_(ds), V_(gs), V_(bs)), theseintermediate parameter values can be saved in a three dimensional tableof V_(ds), V_(gs) and V_(bs), or in a reduced dimensionality table if,say V_(bs) is less important and the user wants to save memory. Thisintermediate quantity table can then be used whenever the parametercomes up. This can be implemented as a command, say .table, to specifythe values)

.table Vds_start, Vds_stop, Vds_step, Vgs_start, Vgs_stop, Vgs_step

or set up structure for the table. Tables can be in even or non-evensteps.

The table can be provided before the simulation from an outside source,such as test data, since it is only for single device and does not needthe netlist. Alternately, a simulation can be run just for producingsuch a table. The table size can be chosen by the user as this is atrade off between memory size and speed/accuracy. However, once thetable is produced it can be saved for future use and not be rebuiltevery time it is required. Additionally, the table can be builtincrementally, with entries added for better resolution. The use oftables can also improve the simulation accuracy. If the table size islarge enough, it will be more accurate than calculating on the fly.

The device degradation characterization means can be embedded into thecircuit simulation of step 107. If a user has their own simulator forstep 107 and source code or interface functions, step 105 can becombined into step 107. The advantage of keeping step 105 separate fromstep 107 is that the steps outside of 107 can be independent ofsimulator type.

Step 107 can be a standard prior art simulation and uses the freshmodel. The possible circuit simulations could, for example, be a SPICEsimulator (such as HSPICE or Spectre) or a timing simulator (such asStarsim or Timemill). As this produces the fresh waveform at all thenodes of the circuit it determines the relative stress on the circuitelements. Memory usage can be minimized by virtue of the screeningprocedure as shown in step 103 and the characterization procedure asshown in step 105 as these reduce the number of waveforms that need tobe stored. If step 107 stands alone, the process is more flexible as itcan be used with the various prior simulators and the other steps can beconnected through the interface as described below.

Using a separate simulator for step 107 is less efficient as it requiresmoving large amounts of data back and forth across the interface. If thesimulation can be merged with other steps, it saves on both the time andstorage required for this transferal. Embedding into the circuitsimulator some, or all, of the functions from the device degradationcharacterization means (step 105), the device degradation estimationmeans (step 109), the device degradation quantization means (step 111),and the circuit netlist generation for aging simulation (step 113) willmake the hot-carrier circuit simulation much more efficient and capable.This would let the whole flow to be performed as a single run,processing the data along with simulator and not requiring storage ofall the other data. This can increase the total speed and capabilitiesof the flow by orders of magnitude. This embedded process can alsocombine the parameterized aged device model as described below.

Step 109 is the device degradation estimation means to establish all ofthe ages for each transistor, or other aged device, specified in thenetlist. The device degradation analysis will be more efficient becausethe relevant storage and computations for the devices pre-specified instep 103 can be skipped. Many devices suffer from multiple agingmechanisms that may have different relative importance depending uponbias conditions or other factors. For devices with multiple hot-carrierdegradation taking effect, these devices will have multiple independentdevice age values each corresponding to one mechanism. These various agevalues will contribute to the total device degradation.

As already noted, the device degradation estimation means can beembedded into the circuit simulator. This may be implemented in themodel evaluation module, but in this case the process depends upon theparticular models employed. In one aspect of the present invention, thedevice degradation estimation means is embedded into the circuitsimulator outside of the model part and is consequently independent ofthe particular models used. This allows newer device models to beincorporated without requiring the device age calculation having toembedded individually for each model.

Some examples of different aging mechanisms are the electron trappingand generation of interface state at the oxide/silicon interface. Inaddition to trapping electrons, the oxide may also capture holes intraps. Due to their differing charge, trapped holes will react to theresultant electric field at a bias level differently from the electrons:If the drain to gate voltage is positive, V_(dg)=V_(d)−V_(g)>0, theholes will migrate towards the gate and the electrons towards the drain.Thus, only holes can jump the interface at this bias, while thesituation is reversed if V_(dg)<0.

At step 111, device degradation can be represented in the new circuitnetlist by using the aged device models, by adding current sources, orboth. In the first case, the elements and connections in the SPICE (orother simulation) netlist are not actually changed, but the aged modelcards are used. As the voltage waveforms supplied to different elementsare not the same, elements that have the same model card in the freshsimulation will generally have different aged model cards as theparameters will now differ. In the second case, connections of thenetlist are changed by introducing current sources between device nodes,with independent current sources accounting for different degradationmechanisms. Examples of models which can be used for these currentsources for MOSFETs are the DeltaMOS, DeltaLogId, and DeltaId modelsdescribed below in the “Modeling and Extraction Methodologies” section.

Adding multiple current sources to represent different degradationmechanisms is shown in FIG. 6 for a MOSFET with multiple sources usedsimultaneously. In this example, for MOSFET 60 which has multiplehot-carrier degradation mechanisms, each mechanism will have acorresponding device age (as shown in step 109), and consequently, acurrent source I_(i) 64-i, 1≦i≦n, will be added in parallel between thesource S 62 and drain D 63. In this case, the aged device is representedin the new netlist by the fresh device between the nodes S′ 62 and D′63′ and the aging effects separated out in the currents running frombetween the original source connection S 62 and the node S′ 62′ tobetween the original drain connection D 63 and the node D′ 63′. Each ofthe multiple current sources,

I _(i) =f _(i)(V _(ds) , V _(gs) , V _(bs) ; P),

is added to cover the different mechanisms, where the functional formdepends on the mechanism and where P represents the parameter set forthe model, such as that described below in the “Modeling and ExtractionMethodologies” section. The functional forms of the various f_(i) willbe from physically based models with parameters set by electrical testdata.

In some case, a single mechanism may be represented by more than onecurrent source. For example, although the channel in a fresh transistormay be symmetric between the source and drain, due to damage at thesilicon-oxide interface this symmetry is lost as the circuit ages.Consequently, the current sources added for the aged device may includeseparate sources for forward and reverse biased conditions.

The continuous value device degradations can be quantized to build theaged device models, to build current sources, or both, so that ratherthan doing the simulation for the continuous aging, it can be done in aseries of quantized steps. For example, say a circuit has a milliontransistors that have the same model card when new. As each of thesewill generally have a different age ranging from zero to a maximumvalue, the aged device simulation would have a million aged cards in thecontinuous case. In the quantized case, the age range from zero to themaximum value is broken up into, say, ten sub-ranges with a single agevalue used for each. Then only the discrete subset of ten model cards isused. The full interval need not be broken up into sub-ranges of uniformsize if better resolution is more important in a particular range. Thecriteria for model quantization can be device age or any deviceparameters (such as I_(ds) at different bias conditions, devicetrans-conductance, threshold voltage, etc.) degradations. The devicedegradation quantization means can be embedded into the circuitsimulator. This step is optional.

In step 113 the aging circuit simulation is run with the differentelements at their respective different aged models. Each of thesimulations of step 113 will generally take significantly less time thanthe simulation already performed for the fresh device in step 107. Thisis because in running step 107, the simulation will record the waveformsat the required nodes. These nodes can be specified for particulardevices in the screening stage. In step 113, only waveforms at the nodesthat are needed for comparison with the fresh waveforms need to bestored. Thus, when doing a simulation for multiple ages in a single run,the ability to share steps 101-107 results in large increase inefficiency even though steps 109-113 must be performed individually foreach age.

The above flow is the so-called “one step aging” circuit reliabilitysimulation, where device ages and degradation are estimated using thefresh waveforms generated in step 107. However, as the circuit ages, thewaveforms at the devices comprising the circuit will change. Therefore,the accuracy of the circuit reliability simulation should be improved ifthe circuit waveforms are updated during the degradation circuitsimulation. This process will be called “gradual aging”.

“Gradual aging” can be realized by adding a loop for steps 107, 109 and111, as shown by the dotted line in FIG. 5, to update the models of thecircuit simulator. Assuming the total circuit stress time is T_(n),e.g., 10 years, T_(n) is divided into N time intervals, [T₀, T₁], [T₁,T₂], . . . , [T_(n-1), T_(n)], where T₀ is zero. The transientsimulation time is T, which is usually much smaller than any above timeintervals, for example 10 μs. In “one step aging”, the circuit waveformfrom [0, T] is projected to the end of T_(n),

${{{Age}\left( T_{n} \right)} = {\frac{T_{n}}{T}{{Age}(T)}}},$

or, for the 10 year, 10 microsecond example,

${{Age}\left( {10\mspace{14mu} {yr}} \right)} = {\frac{10\mspace{14mu} {yr}}{1\mspace{14mu} µ\; s}{{{Age}\left( {1\mspace{14mu} µ\; s} \right)}.}}$

Instead, for gradual aging the projection will now be made for each timeinterval.

At the beginning of each time interval, device models will be updatedaccording to device age values. Circuit simulation 107 will be launchedusing updated device models in each loop, with only the first timeinterval using the fresh device model. Device age and degradation willthen be estimated for each loop in step 109. Device degradation canoptionally be quantized and a new circuit netlist for the next timeinterval will be prepared in step 111. Thus, to make the “gradual aging”more accurate for MOSFET devices, in addition to makingI_(ds)=I_(ds)(t), degraded models for I_(sub), I_(gate), andintermediate values can be used for device degradation calculation. Forexample, in the NMOS hot-carrier aging model example of step 105, age isnow a function of I_(sub)(t) and I_(ds)(t):

${{Age}(t)} = {\sum\limits_{i}{\frac{I_{ds}\left( T_{i} \right)}{WH}\left( \frac{I_{sub}\left( T_{i} \right)}{I_{ds}\left( T_{i} \right)} \right)^{m}\Delta \; {t_{i}.}}}$

This loop will continue until the final time interval is completed.While the flow calculated the device age parameters (H, m) using I_(ds),I_(sub), and so on at step 107 for the fresh simulation, the loop backfrom step 113 uses a differing model at step 107 as I_(ds), I_(sub), andthe other parameters will change with time.

Open Data Interface

FIG. 7 is a block diagram of an open data interface (ODI) for use inhot-carrier or other aging simulations. The interface 203 is connectedbetween the degradation simulator 201 and the user inputs 205. In block205 some of information the user may supply is shown, although not allof these will necessarily be provided in all cases, and in some instancewill be integrated into the simulator as described above with respect tostep 107 of FIG. 5. This interface 203 places the hot-carrier circuitsimulator 201 into the designer's environment, allowing the user tocontrol the calculation of age and other functions by supplying theirown, say, age equations and other models into the simulator through 205to calculate age and degradation equations. This allows the user tocustomize the simulation to their needs.

Referring to block 205 in more detail, user defined data and models(such as device age 209, device degradation 211 and auxiliary functions207) that will be used for device age and degradation calculation anduser defined circuit simulator can communicate with the hot-carriercircuit simulator through ODI (203). The Circuit Simulator 213 can be ofthe SPICE or timing simulator type, or the user's adaptation orequivalent. Device instance and model parameters are passed from thehot-carrier circuit simulator 201 through the ODI 203 to user defineddata 205. For example, if the channel width W of a MOSFET is needed forthe age calculation or the bias conditions are needed for the auxiliaryfunctions, the hot-carrier circuit simulator 201 can provide thesevalues. Similarly, user defined data and the simulation results from theuser defined circuit simulator are passed back to hot-carrier circuitsimulator 201 through ODI 203.

The user can also supply auxiliary functions to replace or supplementthe equations found in the hot-carrier circuit simulator 201. Forexample, I_(gate) and I_(sub) are sample auxiliary functions. Thesimulator will provide default equations, but the user may provideauxiliary function that are lacking or for which the user has aproprietary model that they prefer over the default model for theirapplication. For the example of I_(sub), many different model for thesubstrate current exist and the user may prefer a particular one intheir application, such as described in co-pending U.S. patentapplication Ser. No. 09/661,328, filed on 14 Sep., 2000, entitled“MOSFET Modeling for IC Design Accurate for High Frequencies”, which ishereby incorporated herein by this reference. The user can select whichfunction they supply, just specifying a module for, say, I_(sub), andusing default modules for others.

Input parameters, intermediate and final results can be shared among allthe user defined data, such as passing I_(sub) to I_(g), asI_(g)∝I_(sub). This can also include bias conditions, so that afunction, say, age can now be a function of parameters beyond I_(ds),age→age(I_(ds), V_(ds), V_(gs), V_(bs)), and so on. Multiple userdefined data of the same functionality (such as the device age) can beintegrated with the other user defined data. The user may have multipleequations of how, say, age model is calculated and may call any ofthese. Users have the flexibility to choose any one of them. Userdefined data can also be combined with the internal data in thehot-carrier circuit simulator (201) to fulfill the deviceage/degradation calculation. Again, these can be data that come withdevice or add in some proprietary ones the user has added in. The userdefined data can be incomplete. For any of the user definable data notdefined, internal data will be used. User defined functions can accessintermediate results of circuit simulation, such as the saturationvoltage, V_(dsat), or threshold voltage, V_(th), and not just I_(ds).

Parameterized Aged Device Model

Another approach that can be used to study circuit degradation is theuse of a parameterized device model. This method can be used to replacethe above approach through use of a parameterized model card for each ofthe specified circuit elements, or can be used in a complementaryfashion, with some of devices using the parameterized model as describedbelow and the rest of the devices treated as above. Each model parametercan be formulated as a function of several intermediate quantities thatmeasure device degradation, such as device age or other device parameter(I_(ds), V_(th), G_(m), and so on). We will use device age as an examplehereinafter.

Because aged device parameter is a function of device age, device modelcard can be parameterized with the device age as a parameter. Thisimplies that one model card can be used by devices of different deviceage values. Age value can be quantized to limit the number of ageddevice models if a circuit simulator needs to predetermine the models atthe start of simulation. One sample model card could be expressed as

.model nmos nmos vth0'‘0.7+5*age’,

where vth0 is the model parameter related to the threshold value and theother model parameters are suppressed for simplicity. The functionalform of the parameters, such as the shown linear relation for thethreshold voltage, can either be experimentally determined, or have afunctional form based on physical model with the coefficientsexperimentally determined. The building of age models is described morefully below in the “Modeling and Extraction Methodologies” section.

The circuit simulator can then accept device age as an instanceparameter. One example is listed as follows:

ml 1 2 3 4 nmos W=10 uL=0.25u age=0.01

This age value will be used for calculating aged device modelparameters. To obtain the age values for the devices in the netlist, thesteps 101-109 in the flow of FIG. 5 can still be performed, but thepreparation of the netlist in step 111 is different. The age value canalso be specified.

In simulators that do not support age as an instance parameter, a macroor subcircuit can also be used to prepare aged device model parametersfrom a device age value. An auxiliary program can convert eachdegradable device to a subcircuit call. The advantage of this approachis that currently available circuit simulators widely support thisnetlist style even if they do not accept device age directly as aninstance parameter. The examples of FIG. 8 shows the entry of MOSFET mlin a netlist converted to a subcircuit call Xm1 with the device agevalue of age1. The left and right show two differing results, on theleft converting to a subcircuit to introduce the age and on the right tocompute a parameter (here vth0 as above) from this value. The value ofage1 will be used to prepare the aged device model for ml. The use ofsubcircuits is described more fully in co-pending U.S. patentapplication Ser. No. 09/661,328, filed on 14 Sep., 2000, entitled“MOSFET Modeling for IC Design Accurate for High Frequencies”, that wasincorporated by reference above.

According to another aspect device age calculation and aged device modelparameters can be accomplished inside the model evaluation module foreach device. A circuit simulator contains both an engine to solve thecircuit and the model evaluation module. Rather than compute anexpression such as, say, vth0=‘0.7+5*age’ in the engine, the modelevaluation module can alternately calculate vth0=f(age). A model flagcan be used to control whether the computation of the device age and theaged device model parameter should be carried out. For example, this canbe implemented

.model nmos nmos aging_flag=1

where the other parameters are again suppressed. If the flag is set to1, the aged device model parameter will be calculated based on theparameterized equation. This would occur in the circuit simulation 107and present a more integrated approach to compute I_(ds) and otheroutput values. If the flag is set to 0, the calculation would not occur,as would be the case in simulating the fresh model or when the userprefers to use the full flow of FIG. 5,

Modeling and Extraction Methodologies

This section concerns the individual devices that compose a circuit.This begins with a modeling procedure for device age or degradation of aMOSFET or other device in a SPICE or other simulator. This is thenfollowed by methods for how the device operates when degraded. Theseprocedures are then used to extend the concept of binning to includedegradation. These methods allow a device degradation model developedfrom any one parameter to be applied to other parameters. Specificrelations for a particular embodiment to categorize and incorporate hotcarrier degradation are presented.

FIG. 9 is a flow chart for building a device degradation model, forexample the device age model of a MOSFET, by calculating the “age” or“model age” of the device. More generally, this process can be based onany intermediate quantity indicative of the level of device degradationand not just “age”; but to simplify the terminology, the discussionbelow is mostly discussed in terms of the common case of age. At step901, the devices will be stressed, device parameters will be measured atseveral time intervals. To be concrete, the discussion will use anexemplary embodiment of a MOSFET using the example of an age relationgiven above,

${{\delta \mspace{14mu} {{Age}(t)}} = {\frac{I_{ds}}{WH}\left( \frac{I_{sub}}{I_{ds}} \right)^{m}\delta \; t}},$

where t is the time to stress, H and m are known as the voltageacceleration parameters in the degradation model. The degradation of aparameter P, ΔD_(P), is expressed in the relation

ΔD _(P)=(Age_(P))^(n)=(AR)_(P) ^(n) t ^(n),

where AR is the age rate and P is, for example, current I_(ds),transconductance G_(m) or other measurable parameters. The powerdependence of the degradation, n, is known as the time accelerationparameter and gives the functional relation between time anddegradation. The values for H, m and n depends on what is used for theparameter P, so that in general (H_(P1), m_(P1))≠(H_(P2), m_(P2)) andn_(P1)≠n_(P2), and the conditions under which they are measured. Forexample, digital designs may be worried about driving capabilities underhigher bias and look at ΔIds at saturation, while analog engineers mayworry more about the linear region and so use a lower Vds value tomeasure the device parameter degradation.

A definition of lifetime is also needed. For example, using draincurrent at saturation this could be, say, a 10% degradation:

${\frac{\Delta \; I_{{ds},{sat}}}{I_{{ds},{sat}}}_{{V_{gs} = V_{dd}},{V_{ds} = V_{dd}}}} = {- {0.1.}}$

Thus, if stressed to a −10% degradation under bias condition 1, thiswould result in a lifetime τ1 under this bias, and a lifetime τ2 underbias 2, and so on. Generally, the higher the bias condition, the shorterthe τ value.

At step 903, the user can choose any device parameter (such as Ids underany bias condition), to extract the time acceleration parameter n.Various forms for the functional relation between time and degradationcan also be selected, such as fitting the log(log(degradation)) vs.log(time) relation instead of log(degradation)) vs. log(time) can beused for the parameter extraction. This is described more below as thedelta log Id model.

In the prior, I_(ds) in the saturation or linear region are often usedas the parameter. As noted above, the value of n depends on parameterused. In one aspect of the present invention, the user can select theparameter, such as

$\frac{\Delta \; V_{th}}{V_{th}},\frac{\Delta \; I_{{ds},{sat}}}{I_{{ds},{sat}}},\frac{\Delta \; I_{{ds},{lin}}}{I_{{ds},{lin}}},{\Delta \; V_{th}},{\Delta \; I_{{ds},{sat}}},{\Delta \; I_{{ds},{lin}}}$

and so on to extract n from the ΔD relation. If the functional relationof ΔD˜t^(n) is selected, then a plot of log ΔD versus log t will have aslope n, but in the prior art this acceleration parameter will beassociated with the parameter used, for example n_(Vth). In one aspectof the present invention, during the simulation, only a single ncorresponding to the selected parameter is extracted. Although thisprocess could be performed for multiple parameters, it has been foundthat the behavior of a device can be obtained using only the singleselected parameter. This can either be chosen for convenience or due toits particular relevance. This allows the extraction to be performedonly once and still use the value of n for many different focuses. Thus,although for example n_(ΔVth)≠n_(ΔIds) if these were extracted from theparameters indicated by the subscript, the user can use an arbitrary nwithout loss of accuracy as long as n is from the correct device.

It has also been found that functional forms other than ΔD˜t^(n) for therelation between device degradation and time could yield better resultsin some circumstances. This can be exploited by allowing the user toselect a functional form, ΔD=f(Age,n). In particular, in some cases itis found that log(time) versus log(log(degradation)) is more linear thanversus log(degradation)).

At step 905, the voltage acceleration parameters H and m for the MOSFETdevice degradation or age model will be extracted by consideringmultiple device degradation mechanisms at different bias conditionswhich will improve the accuracy of device degradation calculation. Forthe DeltaMOS and DeltaLogId models discussed below, parameter H can beremoved as its function will be merged with some other terms in themodels. Additionally, the parameter m can keep a constant value such as3.0.

If τ is a lifetime for the device, the values of H and m can beextracted from the relations above between δAge and δt as m will be theslope and H the intercept for a plot of log(τI_(ds)) versuslog(I_(sub)/I_(ds)). The value of n will be from the previous step andthe process is done for several different bias conditions. As the nvalues depend on parameter chosen and bias conditions, so then will mand H.

As noted, in the models developed below, the parameter H need not beextracted, but taken as a constant and absorbed into other parameterssuch as the parameters d1 and d2 in equation (3) below. The parameter mis related to the energy required for a hot carrier to jump into theoxide of the MOSFET. Even if H is not extracted, m can still beextracted and used. Alternately, a value for m can be derived fromphysical principles.

It has been found that the relation between AD and Age is not bestrepresented in many cases by a strict power, but contains differentregions that can be represented in this way. A typical relation betweenlog(ΔD) and Age is shown in FIG. 10. This figure shows that the curve1000 starts off with a slope that gradual rolls off into a “degradationsaturation” region where it flats out to a more or less constant slope.By using the single acceleration parameter as in the prior art, call itno, to present device degradation would use the slope of line 1001 toextract its value. The line 1000 is better approximated by usingdifferent values of n for linear approximations of different portions.As shown in FIG. 10, a good approximation can generally be obtained by afirst acceleration parameter n₁ in the initial region that correspondsto the slope of the line 1011 and a second acceleration parameter n₂ forthe saturation region that corresponds to the slope of the line 1012.

The two regions can be combined in a smooth function that combines thetwo regions. One example is shown below in equations (3) and (11), whichuse the form [(α₁Age^(n1))^(−S)+(α₂Age^(n2))^(−S)]^(−1/S), where theparameters α₁, α₂ are d₁, d₂ in those equations and the smoothing factorS is a positive constant. The value of n is that extracted in step 903and is used to obtain an Age value in a first approximation, which canthen be used to obtain the further values of n such as n₁ and n₂.

At step 907, the parameters n₁ and n₂ will be extracted again toconsider the degradation saturation effect and which will improve theaccuracy. This step is optional since if line 1000 of FIG. 1 isconsidered linear enough, the initial n value could be used.Alternately, this process could of course be extended to beyond the twosegment linear approximation of curve 1000 by further iterations of step907.

Once the degradation model is obtained from one of the variation of theprocess of FIG. 9, the model for the degraded device (such as a SPICEtype model) can be obtained. Two embodiments are presented in FIGS. 11and 14.

FIG. 11 is a flow chart of the first embodiment for building degradeddevice model. At step 1101, the devices will be stressed, and devicecharacteristics and parameters will be measured at several timeintervals. This can be performed at the same time as step 901 above, butmakes additional measurements. In step 901, points were obtained forparameters at the time values; here, curves such as the I-Vcharacteristics at the time values are also measured as these are usedto extract the SPICE or other model. Step 1103 builds the devicedegradation model from the measured device parameters. This is the flowof FIG. 9 above.

In step 1105, fresh and degraded device models are built from themeasured device characteristics and the device degradation level iscalculated for each device model. The fresh and degraded models can bebuilt separately. The model cards are extracted from the respectivefresh and degraded curves, such as those shown in FIG. 12. FIG. 12 showsI_(ds)-V_(ds) curves for different values of the gate voltage V_(gs),where the solid curves represent the fresh device and the broken curvesthe degraded device. The models for the fresh and degraded devices canbe constructed separately. The device age or degradation is calculatedfor each model, and is a function both of degradation level and biasconditions, such as shown in equations (1) and (11).

At step 1107, analytical functions can be used to build the degradeddevice model parameters as a function of device age by fitting the ageddevice model parameter vs. device age curves. Model parameter at any agevalue can then be calculated from the function. With this analyticalfunction, the device model card can be parameterized, with device age asa parameter in circuit netlist. This allows devices with different agevalues can share a same device model.

For example, in a model card there will be model parameters p_(i) withvalues V_(i) that change with age. From the relation between Age andV_(i), a table of p_(i) at the Age values can be built. This situationis shown in FIG. 13, where a set of model cards are shown for Age values0, 1, . . . , n. Each of the parameters p_(i) has corresponding valuesV_(i)0, V_(i)1, . . . , V_(i)n. Through curve fitting or using knownequations, the functional relation p_(i)=f_(i)(Age) is then constructed.As degradation affects different parameters to different degrees, theprocess is generally done only for a relatively small number ofsensitive parameters. These can either be pre-selected in the softwareor user selected.

FIG. 14 is a flow chart of a second embodiment for building degradeddevice model. Referring to FIG. 14, at step 1401, devices will bestressed, device characteristics and parameters will be measured atseveral time intervals. At step 1403, build device age model frommeasured device parameters. These are the same as in steps 1101 and 1103

The second embodiment differs in the next pair of steps. At step 1405,fresh device models are again built from measured device characteristicsand device ages are again calculated for the stressed devices. Unlikestep 1105, it is only the fresh models, and not the degraded models,that are constructed. The age is calculated from the Age=(AR)t relation.

At step 1407, analytical functions can be used to build the aged devicemodel parameters as a function of device age by fitting the measureddevice parameters vs. device age values. Device model parameter at anyage value can be calculated from the function. With this analyticalfunction, device model card can be parameterized, with device age as aparameter in circuit netlist. This allows devices with different agevalues can share a same device model.

Step 1407 is similar to step 1107, but differs in several ways. In thiscase, the result is just the model card for the different ages: that is,rather than have the different values V_(i) for model parameter p_(i) atthe different ages as shown in FIG. 13, only the value for Age=0. Theresult of the process is still a functional relation p_(i)=f_(i)(Age)for model parameters, but without the table of p_(i) versus Age.Instead, it is now derived fitting measured device parameters, such asV_(th), I_(ds,sat), and so on. This uses tables of, say, V_(th) versusAge, I_(ds,sat) versus Age, etc. to fit the curves for these deviceparameters to obtain the functional relation for the selected modelparameters p_(i) through the dependence of the device parameters on themodel parameters. Generally, this method will be more computational thanthat of step 1107.

The techniques of FIGS. 9, 11, and 14 can be combined with the conceptof binning to provide a binning model for degraded devices. FIG. 15 is aflow chart of a first embodiment for building a degraded binning model,with a second embodiment given in FIG. 17. The concept of binning isexplained with FIG. 16.

A particular device may occur in a circuit a number of different timeswith different dimensions. For example, there may be many occurrences ofan NMOS transistor having different dimensions. Rather than providemodel cards for every device, they can be grouped together in “bins”.This is shown in FIG. 16 where the range of width and length values forMOSFETs in a circuit are divided up into smaller regions. All of thedevices within a region are then given the same model card. For example,all of the devices in region 1601, with lengths between A and B andwidths between A and C, are binned together. The grid defining theregions need not have the same number of divisions in the differentdirections and the size of the divisions need not be uniform, but can bechosen for convenience or to provide higher accuracy in a particularrange of values. For example, if the device was relatively immune tolength variations, the grid could have fewer divisions in thisdirection; if the device is more sensitive to changes in length atshorter length, the grid could have finer resolution at short lengths.

To build a model card for a sector, say 1601, the procedure is to go tothe four corners, in this case A, B, C, and D, and construct the modelcards for these dimensions. The card for the sector bound by thesecorners is then formed from a composite of these. Similarly, the cardfor sector 1603 is constructed from devices at the vertices A, B, X, andY.

In one aspect of the present invention, binning techniques are extendedto include degradation. This essentially adds a third dimension ofdevice age or degradation to the usual binning based on width and lengthfound in the prior art for the fresh model. Thus for all of the cornersof a sector, the devices with those dimensions could be stressed and thecorresponding degraded models build, from which the degraded model forthe sector constructed. However, since degradation, and in particularaging due to hot carrier effects, is most pronounced for short channeldevices, it is found in most cases that incorporating aging effects onlyfor devices with minimum channel length is sufficiently accurate. Theexemplary embodiment will follow this approach, although it readilyextends to incorporating degradation effects larger channel lengths ifthe resultant accuracy is worth the increased computation.

Referring to FIG. 15, at step 1501, only devices with minimum channellength, but not necessary all of them, will be stressed, Devices withother channel lengths are assumed to have insignificant hot-carrierdegradations. This is the procedure from steps 901 and 1101 or 1401.Step 1503 builds the device degradation models from the stressed deviceswith minimum L, as is done in the flow of FIG. 9. At step 1505, the ageddevice model using FIG. 11 or/and FIG. 14 flows is built. As describedabove, the result is then p_(i)=f_(i)(Age) for the selected parametersp_(i) for each of the stressed devices. Note that the set of selectedparameters need not be the same for all of the different width values atL_(min), although this will generally be the case.

For the example of region 1601 with devices at both of the L_(min)corners stressed, the result will be p_(i) ^(A)=f_(i) ^(A)(Age) andp_(i) ^(C)=f_(i) ^(C)(Age) for the corners A and C. In the exemplaryembodiment, the devices corresponding to corners B and D are notstressed and p_(i) ^(B), p_(i) ^(D)≠f(Age). From theses, p_(i)^(region)=f_(i) ^(region)(Age) is constructed in step 1507. Ifdegradation is significant for the channel length corresponding to B andD, the degradation can also be incorporated at the cost of morecomputation.

Thus, at step 1507, for any stressed devices, it has an analyticfunction for each aged device model parameters as a function of agevalue. Unstressed devices L_(min) will be skipped in building thebinning model, as described below in the second embodiment discussedwith respect to FIG. 17. For all the devices other than the minimum Ldevices, their aged device models are all the same as theircorresponding fresh ones. The binned model parameters will be ananalytic function of device age.

FIG. 17 is a flow chart of a second embodiment for building a degradedbinning model. At step 1701, only devices with minimum channel length,but not necessary all of them, will be stressed. Devices with otherchannel lengths are assumed to have insignificant hot-carrierdegradations. Their aged device models are all the same as theircorresponding fresh ones. At step 1703, device age model is built fromthe stressed devices with minimum L. These are the same as steps 1501and 1503 above.

Step 1705 builds degraded device models and calculates degradation levelvalues for aged device models, as in step 1405. Step 1707 obtains a setof device age values from all the aged device models of this device. Forexample, picking one of the L_(min) corners, the process builds, say, 10device models for A to get Age₀, Age₁, . . . , Age₁₀ for times t₀, t₁, .. . , t₁₀, where Age₀ at t₀ corresponds to the fresh device.

At step 1709, for any stressed device, a degraded device model of aspecific degradation value will be generated by interpolation orextrapolation from the measured values. Consider the case where forpoint C of FIG. 16 at, say, times t₀, t_(C1), t_(C2), t_(C3), there arethe ages of Age₀, Age_(C1), Age_(C2), Age_(C3). To construct the modelcard for bin 1601 for times t₀, t₁, . . . , t₁₀, the process willgenerate the parameters for C at the 10 values corresponding to t₁, . .. , t₁₀.

The 10 (in this example) new degraded model cards at these times for Cwill be build from the three stressed model at t_(C1), t_(C2), t_(C3).For example, if at Age₁ the device of point A has ΔV_(th)=0.1V, to getthe device at point C with a ΔV_(th) of 0.1V the parameters in the modelcard are adjusted for C at Age_(C1)=Age₁ to get this value. This allowsa set of ten degraded model cards for the bin region, here 1601, to beconstructed. Hence there will be a binned model for each of the 10 agesand an interpolation can be done for the real Age values.

For those unstressed devices, degraded device models can be generated byadjusting parameters in the fresh models to get the same deviceparameter degradations as the stressed devices of the same age value.This allows for a missing L_(min), corner to be built. Alternately,these devices can be skipped in building the binning model, so that if,say, the device at A is skipped, the regions 1601 and 1603 could becombined into a single bin using X, Y, C, and D. At step 1711, the agevalue used in the binning will be the age value for the binned model.

FIGS. 18 and 19 are flow charts for the binning methodology of degradeddevice models based on FIGS. 15 and 17, respectively. These embodimentstreat time in discreet values and describe the use of binning in thesetwo cases. Referring to FIG. 18, step 1801 starts with the degradedbinning model of the flow in FIG. 15. The device age value is suppliedat 1803, and for this value the effective model parameters arecalculated using the model from step 1801.

In the embodiment of FIG. 19, the binning model of FIG. 17 and a deviceage value are supplied at steps 1901 and 1903, respectively. Using thepair of degraded device models with the age values nearest the suppliedage value, effective model parameters are calculated in 1905 using themodel of FIG. 17. The model parameters for the supplied age are theninterpolated or extrapolated at 1907.

As described above, the present invention allows a degradation valuederived from one parameter to be used in obtaining the degradation ofanother device parameter. For example, the Age value in equation (1)below need not be that obtained through measurements on the draincurrent and the Age value in equation (11) below need not be thatobtained through measurements on the threshold voltage. FIG. 20 is aflow chart for generating degradation on any device parameter.

In step 2001, a degradation level value and degraded device model areobtained using any selected device parameter, such as I_(ds), V_(th),G_(m), and so on. From this, the degraded device characteristics aregenerated using the Age value and generating the device characteristics,such as the I-V curves, in step 2003. In step 2005, the degradation ofany device parameter can be extracted.

Thus, the method allows use of, say, ΔV_(th) or ΔG_(m) to calculate anacceleration parameter n characterized accordingly. As the value of ndiffers for different parameters, it will generally be the case thatn_(V) _(th) ≠n_(I) _(ds) ≠n_(G) _(m) ≠ . . . , and the practice in theprior art is to use n_(V) _(th) to generate ΔV_(th), n_(Ids) to generateΔI_(ds), nG_(m) to generate ΔG_(m), and so on. Consequently, if a userwanted both, say, ΔV_(th) and ΔG_(m), two separate calculations would berun. According to the present invention, using only a single parameter,say n_(Vth) can be used not just for ΔV_(th), but also ΔG_(m), ΔI_(ds),etc. This is done by extracting device parameters from the devicebehavior, such as the I-V curves, instead of just using the equations ofeach of the parameters.

DeltaMOS Model and DeltaLogId Model

As described above, a degraded device can be represented either in aSPICE or other simulator, or through representing the degraded device byusing a fresh model with elements to incorporate the aging external tothe fresh device, such as in FIG. 6. In this latter approach, the freshdevice is not aged, although the two approaches can be combined. This isa unified compact scalable DeltaMos model for accurate hot-carrierreliability circuit simulation based on the equations below. Thissection also expands and enhances this procedure, for example addingexternal voltage sources as well as current sources.

Strong dependencies on oxide electric field E_(ox) and body bias Vbsshould be incorporated into the model for accuracy as shown in Equation(1):

$\begin{matrix}{{\frac{\Delta \; I_{ds}}{I_{{ds}\; 0}} = {\frac{\Delta \; I_{{ds},l}}{I_{{ds},{l\; 0}}}\left( {V_{gs},V_{bs},{Age}} \right)*{F\left( {V_{gs},V_{ds}} \right)}}},} & (1)\end{matrix}$

where I_(ds,1) is the drain-source current in the linear region. Asdescribed above, it also improves the smooth transition fromsubthreshold region to linear region and to saturation region. One formof the implementation can refer to Equation. (2-6). The E_(ox) effect isreflected in the V_(gsteff)/T_(ox) term.

$\begin{matrix}{{F\left( {V_{gs},V_{ds}} \right)} = {\frac{1}{1 + {\exp\left( \frac{V_{ds} - {a_{1}*V_{gs}} - a_{2}}{{b_{1}*V_{gs}} + b_{2}} \right)}} + \left( {{c_{1}*V_{gs}} + c_{2}} \right)}} & (2) \\{{\frac{\Delta \; I_{{ds},l}}{I_{{ds},{l\; 0}}}\left( {V_{gs},V_{bs},{Age}} \right)} = {\frac{1}{l_{eff}}*\begin{bmatrix}{\left( {d_{1{eff}}\left( {V_{gs},V_{bs}} \right)*{Age}^{n\; 1}} \right)^{s} +} \\\left( {{d_{2{eff}}\left( {V_{gs},V_{bs}} \right)}*{Age}^{n\; 2}} \right)^{- S}\end{bmatrix}^{{- 1}/S}}} & (3)\end{matrix}$

This form shows the use of multiple acceleration parameters describedwith respect to step 907 of FIG. 9.

$\begin{matrix}{{d_{1{eff}}\left( {V_{gs},V_{bs}} \right)} = \frac{d_{10}*C_{f}}{\begin{matrix}{1 + {\left( {d_{1a} + {d_{1c}*V_{bs}}} \right)*\frac{V_{gsteff}\left( {V_{gs},V_{bs}} \right)}{T_{ox}}} +} \\{d_{1b}*\left( \frac{V_{gsteff}\left( {V_{gs},V_{bs}} \right)}{T_{ox}} \right)^{2}}\end{matrix}}} & (4) \\{{d_{2{eff}}\left( {V_{gs},V_{bs}} \right)} = \frac{d_{20}*C_{f}}{\begin{matrix}{1 + {\left( {d_{2a} + {d_{2c}*V_{bs}}} \right)*\frac{V_{gsteff}\left( {V_{gs},V_{bs}} \right)}{T_{ox}}} +} \\{d_{2b}*\left( \frac{V_{gsteff}\left( {V_{gs},V_{bs}} \right)}{T_{ox}} \right)^{2}}\end{matrix}}} & (5)\end{matrix}$

The asymptote functions can be introduced to better model thecoefficients d_(1eff) and d_(2eff), with one form of the implementationin Equations (4), (5), (7), and (8).

$\begin{matrix}{{V_{gsteff}\left( {V_{gs},V_{bs}} \right)} = \frac{2*s_{f\; 1}*V_{tm}*{\ln \begin{bmatrix}{1 + {\left( {s_{f\; 0} + {d_{b}*V_{bs}}} \right)*}} \\{\exp \left( \frac{V_{gs} - V_{{th}\; 0}}{2*s_{f\; 1}*V_{tm}} \right)}\end{bmatrix}}}{1 + {\left( {s_{f\; 0} + {d_{b}*V_{bs}}} \right)*{\exp \left( \frac{V_{{th}\; 0} - V_{gs}}{2*s_{f\; 1}*V_{tm}} \right)}}}} & (6) \\{{{where},{{if}\mspace{14mu} \left( {{C_{ft}^{2} + {4*d_{a}}}>=0} \right)},\mspace{101mu} {{C_{f}\left( V_{gs} \right)} = {{0.5*\left( {{C_{ft}\left( V_{gs} \right)} - \sqrt{{C_{ft}({Vgs})}^{2} + {4*d_{a}}}} \right)} + 1}}}{{{else}\mspace{20mu} C_{f}} = {0\mspace{14mu} {and}}}} & (7) \\{{C_{ft}\left( V_{gs} \right)} = {{2*V_{tm}*{\ln \left\lbrack {1 + {c_{f\; 0}*{\exp\left( \frac{V_{gs} - V_{th} - v_{off}}{c_{f\; 1}*V_{tm}} \right)}}} \right\rbrack}} - 1}} & (8)\end{matrix}$

Bias dependency of n1 and n2 improves the accuracy. V_(gs) and V_(ds)dependencies can be separated. One form of the implementation is shownin Equations (9) and (10):

$\begin{matrix}{n_{1} = {n_{10}\frac{1 - {n_{11}*{\exp \left( {{- n_{1d}}*V_{ds}} \right)}}}{1 + {n_{1g}*V_{gsteff}}}}} & (9) \\{n_{2} = {n_{20}\frac{1 - {n_{21}*{\exp \left( {{- n_{2d}}*V_{ds}} \right)}}}{1 + {n_{2g}*V_{gsteff}}}}} & (10)\end{matrix}$

The use of (d₁,n1) and (d₂,n2) let the single Age be used regardless ofthe parameter from which it was obtained.

Threshold voltage degradation can be included. One form of theimplementation is shown in Equations (11-18), which are similar to theI_(d) degradation equations as shown in Equations (3-10). Below,ΔV_(th)=V_(th)−V_(th0) where V_(th) is the degraded threshold voltageand V_(th0) is the fresh threshold voltage.

$\begin{matrix}{{\frac{\Delta \; V_{th}}{V_{{th}\; 0}}\begin{pmatrix}{V_{gs},V_{bs},} \\{Age}\end{pmatrix}} = {\frac{1}{l_{eff}}*\begin{bmatrix}{\left( {{d_{3{eff}}\left( {V_{gs},V_{bs}} \right)}*{Age}^{n_{3}}} \right)^{- s_{1}} +} \\\left( {{d_{4{eff}}\left( {V_{gs},V_{bs}} \right)}*{Age}^{n_{4}}} \right)^{- s_{1}}\end{bmatrix}^{{- 1}/s_{1}}}} & (11) \\{{d_{3{eff}}\left( {V_{gs},V_{bs}} \right)} = \frac{d_{30}*C_{f\; 1}}{\begin{matrix}{1 + {\left( {d_{3a} + {d_{3c}*V_{bs}}} \right)*\frac{V_{{gsteff}\; 1}\left( {V_{gs},V_{bs}} \right)}{T_{ox}}} +} \\{d_{3b}*\left( \frac{V_{{gsteff}\; 1}\left( {V_{gs},V_{bs}} \right)}{T_{ox}} \right)^{2}}\end{matrix}}} & (12) \\{{d_{4{eff}}\left( {V_{{gs},}V_{bs}} \right)} = \frac{d_{40}*C_{f\; 1}}{\begin{matrix}{1 + {\left( {d_{4\; a} + {d_{4c}*V_{bs}}} \right)*\frac{V_{{gsteff}\; 1}\left( {V_{gs},V_{bs}} \right)}{T_{ox}}} +} \\{d_{4b}*\left( \frac{V_{{gsteff}\; 1}\left( {V_{gs},V_{bs}} \right)}{T_{ox}} \right)^{2}}\end{matrix}}} & (13) \\{{V_{{gsteff}\; 1}\left( {V_{gs},V_{bs}} \right)} = \frac{2*s_{f\; 3}*V_{im}*{\ln \begin{bmatrix}{1 + {\left( {s_{f\; 2} + {d_{b\; 1}*V_{bs}}} \right)*}} \\{\exp \left( \frac{V_{gs} - V_{{th}\; 0}}{2*s_{f\; 3}*V_{tm}} \right)}\end{bmatrix}}}{1 + {\left( {s_{f\; 2} + {d_{b\; 1}*V_{bs}}} \right)*{\exp \left( \frac{V_{{th}\; 0} - V_{gs}}{2*s_{f\; 3}*V_{tm}} \right)}}}} & (14) \\{{{where},{{if}\mspace{14mu} \left( {{C_{{ft}\; 1}^{2} + {4*{da}\; 1}}>=0} \right)}}{{C_{f\; 1}\left( V_{gs} \right)} = {{0.5*\left( {{C_{{ft}\; 1}\left( V_{gs} \right)} - \sqrt{{C_{{ft}\; 1}({Vgs})}^{2} + {4*d_{a\; 1}}}} \right)} + 1}}{{{else}\mspace{14mu} C_{f\; 1}} = 0}} & (15) \\{{C_{{ft}\; 1}\left( V_{gs} \right)} = {{2*V_{tm}*{\ln \left\lbrack {1 + {c_{f\; 2}*{\exp \left( \frac{V_{gs} - V_{{th}\; 0} - v_{{off}\; 1}}{c_{f\; 3}*V_{tm}} \right)}}} \right\rbrack}} - 1}} & (16) \\{n_{3} = {n_{30}\frac{1 - {n_{31}*{\exp \left( {{- n_{3d}}*V_{ds}} \right)}}}{1 + {n_{3g}*V_{{gsteff}\; 1}}}}} & (17) \\{n_{4} = {n_{40}\frac{1 - {n_{41}*{\exp \left( {{- n_{4d}}*V_{ds}} \right)}}}{1 + {n_{4g}*V_{{gsteff}\; 1}}}}} & (18)\end{matrix}$

In these equations, V_(tm) is the thermal voltage (Kt/q) and thefollowing are all model parameters:

-   -   a₁, a₂, b₁, b₂, c₁, c₂, n₁₀, n₁₁, n_(1g), n_(1d), n₂₀, n₂₁,        n_(2g), n_(2d), s, d₁₀, d_(1a), d_(1b), d_(1c), d₂₀, d_(2a),        d_(2b), d_(2c), S_(f0), s_(f1), c_(f0), c_(f1), v_(off), d_(a),        d_(b); n₃₀, n₃₁, n_(13g), n_(3d), n₄₀, n₄₁, n_(4g), n4d, s1,        d₃₀, d₃₀, d_(3a), d_(3b), d_(3c), d₄₀, d_(4a), d_(4b), d_(4c),        s_(f2), s_(f3), c_(f02), c_(f3), v_(off1), d_(a1), d_(b1)

The I_(ds) degradation can be incorporated into aging circuit simulationby adding a current source in parallel to the MOSFET channel for eachIds degradation component of the device as described with respect toFIG. 6 above. The value I_(d) is as seen from external to the circuit,I_(ds0) is the fresh device value, and ΔI_(ds)=I_(ds)−I_(ds0). TheV_(th) equations can be similarly incorporated.

Before, a fresh model card was used with a current source with magnitudeΔI_(ds) connected between the source and drain terminals. The model cardcan also be changed to include V_(th) degradation by incorporating,either instead or additionally, a voltage source with magnitude ΔVconnected to a terminal of the fresh device. FIG. 21 shows an exemplaryembodiment. Also, it should be noted that if V_(th) changes, so willother parameters, such as intrinsic capacitor parameters and so on.

FIG. 21 shows a MOSFET 2000 which has a voltage source ΔV_(th) 2004added between the gate and the gate terminal G 2001. The aged device isrepresented in the netlist by the fresh device (between the nodes G′2001′, S′ 2002′ and D′ 2003′) and the aging effects separated out in thevoltage source 2004 between the original gate connection G 2001 and thenode G′ 2001′. The original source and drain are unchanged in thisexample, so that S, D and the same as S′, D′.

Thus, the V_(th) degradation can also be considered into aging circuitsimulation by adding a voltage source at one device terminal or bymodifying the threshold voltage parameters in the model cards. This willhelp to improve the model accuracy as it also considers other devicedegradations such as the intrinsic capacitance degradation, in additionto the Id degradation. One or more such voltage sources can be combinedwith the current sources of FIG. 6. In particular, it is often the casethat the one or more of the current sources is a function of thethreshold voltage, I_(i)=f_(i)(V_(th)). This V_(th) can be separated outby placing a voltage source as in FIG. 21 in combination with thecurrent source as in FIG. 6 which is no longer dependent on thethreshold voltage, I_(i)≠f_(i)(V_(th)).

As noted in the discussion of step 903 of FIG. 9, different functionalforms may be selected. One example is the DeltaLogId Model usingLog(I_(ds)/I_(ds0)), instead of ΔI_(ds)/I_(ds0) to formulate hot-carrierdegradation in MOSFET transistors. As before, ΔI_(ds)=I_(ds)−I_(ds0),where I_(ds0) and I_(ds) are fresh and degraded drain current,respectively. All the model equations are the same as that of DeltaMosmodel, except all the I_(ds)/I_(ds0) terms are changed toLog(I_(ds)/I_(ds0)). Of course, all the model parameters are different.This approach is called the DeltaLogId model.

ΔI_(ds) can be deduced from Log(I_(ds)/I_(ds0)) equation[ΔI_(ds)=(exp(log(I_(ds)/I_(ds0)))−1)*I_(ds0)] and can be used to addcurrent source for the aging circuit simulation which is similar to theDeltaMos model. Threshold voltage degradation can also be included forthe DeltaLogId model which is similar to the DeltaMOS model. UsingLog(I_(ds)/I_(ds0)) for building device age model has been shown in step903 of FIG. 9.

Application Domains

It is well known in the art that logic or digital systems and/or methodscan include a wide variety of different components and differentfunctions in a modular fashion. The following will be apparent to thoseof skill in the art from the teachings provided herein. Differentembodiments of the present invention can include different combinationsof elements and/or functions. Different embodiments of the presentinvention can include actions or steps performed in a different orderthan described in any specific example herein. Different embodiments ofthe present invention can include groupings of parts or components intolarger parts or components different than described in any specificexample herein. For purposes of clarity, the invention is described interms of systems that include many different innovative components andinnovative combinations of innovative components and known components.No inference should be taken to limit the invention to combinationscontaining all of the innovative components listed in any illustrativeembodiment in this specification. The functional aspects of theinvention, as will be understood from the teachings herein, may beimplemented or accomplished using any appropriate implementationenvironment or programming language, such as C++, COBOL, Pascal, Java,Java-script, etc. All publications, patents, and patent applicationscited herein are hereby incorporated by reference in their entirety forall purposes.

The present invention is presented largely in terms of procedures,steps, logic blocks, processing, and other symbolic representations thatresemble data processing devices. These process descriptions andrepresentations are the means used by those experienced or skilled inthe art to most effectively convey the substance of their work to othersskilled in the art. The method along with the system to be described indetail below is a self-consistent sequence of processes or steps leadingto a desired result. These steps or processes are those requiringphysical manipulations of physical quantities. Usually, though notnecessarily, these quantities may take the form of electrical signalscapable of being stored, transferred, combined, compared, displayed andotherwise manipulated in a computer system or electronic computingdevices. It proves convenient at times, principally for reasons ofcommon usage, to refer to these signals as bits, values, elements,symbols, operations, messages, terms, numbers, or the like. It should beborne in mind that all of these similar terms are to be associated withthe appropriate physical quantities and are merely convenient labelsapplied to these quantities. Unless specifically stated otherwise asapparent from the following description, it is appreciated thatthroughout the present invention, discussions utilizing terms such asprocessing or computing or verifying or displaying or the like, refer tothe actions and processes of a computing device that manipulates andtransforms data represented as physical quantities within the device'sregisters and memories into analog output signals via residenttransducers.

Many aspects of the methods of the present invention will most commonlybe implemented in software as a computer program product, although manyof these can be implemented in hardware or by a combination of softwareand hardware. As will be understood in the art, the invention orcomponents thereof may be embodied in a fixed media program componentcontaining logic instructions and/or data that when loaded into anappropriately configured computing device cause that device to performaccording to the invention. As will be understood in the art, a fixedmedia program may be delivered to a user on a fixed media for loading ina users computer or a fixed media program can reside on a remote serverthat a user accesses through a communication medium in order to downloada program component. Examples of such fixed media include a disk-typeoptical or magnetic media, magnetic tape, solid state memory, etc. Theinvention may be embodied in whole or in part as software recorded onthis fixed media.

The invention also may be embodied in whole or in part within thecircuitry of an application specific integrated circuit (ASIC) or aprogrammable logic device (PLD). In such a case, the invention may beembodied in a computer understandable descriptor language which may beused to create an ASIC or PLD that operates as herein described.

Although the various aspects of the present invention have beendescribed with respect to specific exemplary embodiments, it will beunderstood that the invention is entitled to protection within the fullscope of the appended claims.

1. A method of obtaining a device degradation model, comprising:stressing the device for a time period; measuring values for a pluralityof device parameters of the stressed device during the time period;selecting one of the device parameters; extracting a relation betweenstress time and the degradation of the selected parameter from themeasured values for the selected parameter during the time period;extracting a degradation rate for the device from the relation betweenstress time and the degradation of the selected parameter; deriving fromthe degradation rate a device degradation model for a device parameterother than the selected device parameter.
 2. The method of claim 1,wherein the selected device parameter is source drain current.
 3. Themethod of claim 1, wherein the selected device parameter is thresholdvoltage.
 4. The method of claim 1, wherein the selected device parameteris transconductance.
 5. The method of claim 1, wherein the deriving fromthe degradation rate a device degradation model comprises: determiningthe dependence of the device parameter other than the selected deviceparameter upon the degradation rate.
 6. The method of claim 5, whereinthe extracting a relation between stress time and the degradation of theselected parameter comprises: determining a first time accelerationparameter; and wherein the determining the dependence of the deviceparameter other than the selected device parameter upon the degradationrate comprises determining one or more second time accelerationparameters.
 7. The method of claim 6, wherein the number of second timeacceleration parameters is two.
 8. The method of claim 1, furthercomprising: prior to extracting a relation between stress time and thedegradation of the selected parameter, selecting a functional form forthe relation.
 9. The method of claim 8, wherein said functional form isthat the degradation is proportional to the stress time to a power. 10.The method of claim 8, wherein said functional form is that thelogarithm of the degradation is proportional to the stress time to apower.
 11. A computer readable storage device embodying a program ofinstructions executable by a computer to perform the method of claim 1.12. (canceled)
 13. A method of obtaining a device degradation model,comprising: stressing the device for a time period; measuring values fora plurality of device parameters of the stressed device during the timeperiod; selecting from a plurality of functional forms a functional formfor the time dependence of degradation of one of the device parameters;extracting a relation between stress time and the degradation of saidone of the device parameters from the measured values for the selectedparameter during the time period using the selected functional form; andderiving a device degradation model from the relation between stresstime and the degradation of said one of the device parameters.
 14. Themethod of claim 13, wherein said functional form is that the degradationis proportional to the time to a power.
 15. The method of claim 13,wherein said functional form is that the logarithm of the degradation isproportional to the time to a power.
 16. The method of claim 13, whereinsaid extracting a relation between stress time and the degradationcomprises determining a degradation rate, and wherein the devicedegradation model is a function of the degradation rate.
 17. The methodof claim 16, wherein said determining a degradation rate includesspecifying the power of the ratio of the substrate current and thesource to drain current upon which the degradation rate depends.
 18. Themethod of claim 16, wherein the degradation rate is only specified up toa proportionality constant.
 19. The method of claim 16, wherein thederiving a device degradation model comprises: determining thedependence said one of the device parameters upon the degradation rate.20. The method of claim 19, wherein the extracting a relation betweenstress time and the degradation of the selected comprises: determining afirst time acceleration parameter; and wherein the determining thedependence said one of the device parameters upon the degradation ratecomprises determining one or more second time acceleration parameters.21. The method of claim 20, wherein the number of second timeacceleration parameters is two.
 22. A computer readable storage deviceembodying a program of instructions executable by a computer to performthe method of claim
 13. 23. A method for transmitting a program ofinstructions executable by a computer to perform a process of simulatingthe degradation of a circuit, said method comprising: causing thetransmission of a program of instructions to a client device, therebyenabling the client device to perform, by means of such program, theprocess of the method of claim
 13. 24-32. (canceled)
 33. A method ofobtaining a degraded device model, comprising: stressing the device fora time period; measuring values for device parameters and devicecharacteristics of the stressed device during the time period; buildinga device degradation model of the device using the measured deviceparameter values; building a fresh model for the device from themeasured device characteristic values; building from the measured devicecharacteristic values a degraded model for the device corresponding to avalue in the time period device; obtaining an intermediate quantity fromthe device degradation model and the measured device characteristicvalues; and obtaining a relation for a model parameter as a function ofthe intermediate quantity from the fresh and degraded models.
 34. Themethod of claim 33, wherein the device is a MOSFET and the devicecharacteristics include the current-voltage behavior.
 35. The method ofclaim 33, wherein the obtaining a relation for a model parameter as afunction of the intermediate quantity comprises fitting the degradedmodel parameter versus device age curves.
 36. The method of claim 33,further comprising: obtaining a model for the device incorporating therelation for the model parameter as a function of the intermediatequantity.
 37. A computer readable storage device embodying a program ofinstructions executable by a computer to perform the method of claim 33.38. A method for transmitting a program of instructions executable by acomputer to perform a process of simulating the degradation of acircuit, said method comprising: causing the transmission of a programof instructions to a client device, thereby enabling the client deviceto perform, by means of such program, the process of the method of claim33.
 39. A method of obtaining a degraded device model, comprising:stressing the device for a time period; measuring values for deviceparameters and device characteristics of the stressed device during thetime period; building a device degradation model of the device using themeasured device parameter values; building a fresh model for the devicefrom the measured device characteristic values; obtaining anintermediate quantity from the device degradation model and the measureddevice characteristic values; obtaining a relation for a deviceparameter as a function of the device age from the fresh model, theintermediate quantity, and measured parameter values; and obtainingrelation for a model parameter as a function of the intermediatequantity from the relation for a device parameter as a function of theintermediate quantity.
 40. The method of claim 39, wherein the device isa MOSFET and the device characteristics include the current-voltagebehavior.
 41. The method of claim 39, wherein the device is a MOSFET andthe device parameter is the source drain current.
 42. The method ofclaim 39, wherein the device is a MOSFET and the device parameter is thetransconductance.
 43. The method of claim 39, wherein the device is aMOSFET and the device parameter is the threshold voltage.
 44. The methodof claim 39, wherein the obtaining a relation for a device modelparameter as a function of the intermediate quantity comprises fittingthe measured device parameters versus device age.
 45. The method ofclaim 39, further comprising: obtaining a model for the deviceincorporating the relation for the model parameter as a function of theintermediate quantity.
 46. A computer readable storage device embodyinga program of instructions executable by a computer to perform the methodof claim
 39. 47. A method for transmitting a program of instructionsexecutable by a computer to perform a process of simulating thedegradation of a circuit, said method comprising: causing thetransmission of a program of instructions to a client device, therebyenabling the client device to perform, by means of such program, theprocess of the method of claim
 39. 48. A method of obtaining a degradeddevice model, comprising: providing non-degraded models for the deviceat a plurality of widths for a plurality of lengths; determining adegraded device model for the device at the plurality of widths for theminimum length of the plurality of the lengths; and for the devicehaving a length between the minimum length and a second of the lengthsand having a width between a first and a second of the widths,generating a degraded device model from the non-degraded device modelsat the minimum length and second of the lengths for the first and secondwidths and from the degraded device model models at the minimum lengthfor the first and second widths.
 49. The method of claim 48, wherein thedetermining comprises: stressing the device for the plurality of widthsfor the minimum length for a period of time; measuring values forparameters and characteristics of the stressed device during the timeperiod; building device degradation models for the stressed device usingthe measured parameter values; and building the degraded device modelsfor the devices from device degradation models for the device at theplurality of widths for the minimum length.
 50. The method of claim 49,wherein the building the degraded device models comprises: buildingdegraded device models for the first width at the minimum length at afirst set of degradation levels; and building degraded device models forthe second width at the minimum length at a second set of degradationlevels, wherein the first set of degradation levels is different thanthe second set of degradation levels; and determining degraded devicemodels for the second width at the minimum length at the first set ofdegradation levels from the degraded device models for the second widthat the minimum length at a second set of degradation levels.
 51. Acomputer readable storage device embodying a program of instructionsexecutable by a computer to perform the method of claim
 48. 52.(canceled)
 53. A method of obtaining the degradation level of a firstdevice parameter of a device, comprising: obtaining an age value for thedevice from a second device parameter, wherein the second deviceparameter is different than said first device parameter; generating thedegraded characteristics of the device using the device degradationvalue; and extracting the degradation level of the first deviceparameter from the degraded characteristics of the device.
 54. Themethod of claim 53, wherein generating the degraded characteristics ofthe device comprises: producing a degraded device model card using thedevice degradation value; and using the degraded device model card tosimulate the degraded characteristics of the device.
 55. The method ofclaim 53, wherein extracting the degradation level of the first deviceparameter comprises: expressing the degradation level of the firstdevice parameter as a function of the age value.
 56. The method of claim55, wherein the function is of the form of the age value raised to apower. 57-69. (canceled)